1. Field of the Invention
The present invention relates to an integrated circuit for delivering a clock signal, and more particularly to the management of the current consumption of this integrated circuit.
2. Description of the Related Art
An integrated circuit described in U.S. Pat. No. 5,210,846 has a “one wire” communication interface controlled by a data send-receive protocol allowing data to be conveyed on a single wire in semi-duplex mode, while sending a clock signal.
An example of such an integrated circuit 10 having a “one wire” communication interface is represented in FIG. 1. The integrated circuit 10 includes a communication terminal 11, a ground terminal 12, a clock extraction circuit CEC1 delivering a clock signal CK1 and a data extraction circuit DEC delivering data DTIN, the circuits CEC1 and DEC both being connected to the terminal 11 at input. The integrated circuit 10 also has a protocol control circuit PCC, registers with serial input and parallel output or parallel input and serial output, schematically represented in the shape of a register bank REGB, and a memory MEM. The memory MEM is of FLASH, EEPROM, ROM or RAM type or comprises a combination of these different types of memory. The clock signal CK1 delivered by the circuit CEC1 is applied to the circuit DEC and to the protocol control circuit PCC. In addition to executing the communication protocol, the circuit PCC also controls the registers of the bank REGB and read and write controls the memory MEM.
The data DIN delivered by the circuit DEC are stored in registers of the bank REGB before being processed. They are, for example, commands (operation codes), addresses of data to be saved or to be read in the memory MEM, or data to be saved in the memory.
The integrated circuit 10 also comprises means for sending data DTOUT, mainly comprising a switch connected between the terminal 11 and the ground, such as a MOS transistor TN1 for example, and an inverting gate INV1 the output of which drives the control terminal (gate) of the switch transistor TN1. The input of the gate INV1 is linked to the serial output of a register of the register bank REGB. The data likely to be sent are for example data read in the memory MEM or messages from the circuit PCC bound for the controller.
A controller CNTR, intended to exchange data with the integrated circuit 10, is also represented in FIG. 1. The terminal 11 of the integrated circuit 10 is connected to a corresponding terminal 11′ of the controller CNTR, and the ground terminal 12 is connected to a corresponding terminal 12′ of the controller.
The bidirectional exchange of data in semi-duplex mode between the integrated circuit 10 and the controller CNTR is based on a shared control of the value of the signal DT present on the “one wire” communication interface, i.e., here the terminal 11 of the integrated circuit 10 and the terminal 11′ of the controller CNTR. The controller comprises a pull-up resistor R1 that imposes a voltage Vcc representing the logic value 1 on the communication interface. Data DTX are sent by the controller through an open-drain inverting gate INV2 (that only imposes the low level) receiving the data DTX at input. Data DTR are received by the controller through an inverting gate INV3 connected to the terminal 11′ at input. Data DTOUT are sent by the integrated circuit 10 through the switch TN1, the series resistance of which in the on state RDSON is much lower than the resistor R1.
FIGS. 2A, 2B represent the appearance of the signal DT respectively upon the receiving of data and upon the sending of data by the integrated circuit 10. FIG. 2C represents the appearance of the clock signal CK1 delivered by the circuit CEC1. Whether in data send or receive mode, the signal DT always has time slots TS delimited by falling edges of the signal DT, which are imposed by the controller. In each time slot a sampling window SW is provided for receiving or sending a datum. In data receive mode (FIG. 2A, DT=DTX) the value of the signal DT in the window SW is imposed by the controller, by means of the inverting gate INV2 (bit on 0) and of the resistor R1 (bit on 1). In data send mode (FIG. 2B, DT=DTOUT) the value of the signal DT in the window SW is imposed by the integrated circuit (dotted lines) thanks to the switch transistor TN1, which can be in the on (bit on 0) or off (bit on 1) state. The clock signal CK1 delivered by the clock extraction circuit CEC1 has a clock pulse after each falling edge of the signal DT, the clock pulse being sent inside the sampling window SW.
This integrated circuit has the advantage of only requiring two electric contacts, one for the signal DT and the other for the ground, and is found in various applications in the field of electronic tokens, one side of a token being used for example as a communication terminal 11 and the other as a ground terminal 12, as described in the above-mentioned U.S. Pat. No. 5,210,846.
One disadvantage of this type of application lies in the need to electrically power the integrated circuit. Thus, in a token, a place must be provided to arrange, in addition to the integrated circuit, an electric cell 13, such as a button cell for example, delivering a voltage Vcci for powering the integrated circuit.